Conventionally, a method for detection of video switchover by detecting out of lock of a phase-locked loop circuit (hereinafter referred to as a PLL circuit) by using a PLL circuit, as a method for detecting switchover of video signals. Such methods for detecting out of lock of a PLL circuit includes a method for monitoring a voltage (hereinafter referred to as a VCO control voltage) to be applied to control a voltage-controlled oscillator (hereinafter referred to as a VCO) The VCO control voltage is typically an output of a low-pass filter. The low-pass filter includes a capacitor so that re-charging/discharging of the low-pass filter takes time and not fit for apparatus that requires high-speed operation. In order to offset this disadvantage, methods have been proposed for detecting the dislocation amount of a synchronization signal for an input signal against a reference signal and detecting out of lock based on the dislocation amount of the phase, as described in the Japanese Patent Laid-Open No. 55161/1998 and the Japanese Patent Laid-Open No. 301526/1998.
FIG. 5 is a block diagram showing an configuration example of a related art video switchover detection circuit. The video switchover detection circuit comprises a phase comparator 51, a low-pass filter (hereinafter referred to as an LPF) 52, a voltage-controlled oscillator (hereinafter referred to as a VCO) 53, and a frequency divider 54, and constitutes a PLL circuit with these circuits 51 through 54. As input signals, an external HD that is a pulse obtained by extracting and shaping a horizontal synchronization signal for a video signal and an external VD obtained by extracting and shaping a vertical synchronization signal are input. In the description that follows, a circuit that detects out of lock in the horizontal synchronization signal is called an H system and a circuit that detects out of lock in the vertical synchronization signal is called a V system.
For each of the H and V systems, there are provided reset signal generating circuit 55, 59, counters 56, 60, window setting circuits, 57, 61 and decision circuits 58, 62, respectively. The window setting circuit 57 and the decision circuit 58 compose an H system synchronization decision section 63. The window setting circuit 61 and the decision circuit 62 compose an V system synchronization decision section 64. Further, there is provided an output circuit 65 composed of an OR circuit that outputs as a video switchover detection signal the output of the synchronization decision sections 63, 64.
In the PLL circuit, the output of a phase comparator 51 is input to the VCO 53 via the LPF 52 to cause the VCO 53 to oscillate. The oscillation signal obtained is multiplied by 1/N by using the frequency divider 54 to generate an internal HD serving as a reference signal.
To detect out of lock in the horizontal synchronization signal, the output pulses of the VCO 53 are counted as a clock by the counter 56, and the lock state of the horizontal synchronization signal is determined by the synchronization decision section 63 based on the counter value of the counter 56. In this practice, the internal HD and the output of the VCO 53 are input to the reset signal generating circuit 55. A reset signal is generated based on the corresponding signal timings and input to the reset terminal of the counter 56. As a result, the counter 56 is reset based on the timing of the internal HD. The output pulses of the VCO 53 are counted by the counter 56 and the counter value is input to the synchronization decision section 63.
In the synchronization decision section 63, the window setting circuit 61 sets the window period for determining the lock state and the decision circuit 58 references the count value at the leading edge of the external HD and determined whether the timing at the leading edge of the external HD is within a predetermined widow period in relation to the internal HD. The synchronization decision section 63 detects the dislocation amount of the external HD against the internal HD. In case the dislocation amount has exceeded a predetermined value, the horizontal synchronization signal is assumed as out of synchronization and an out-of-lock detection signal is output.
To detect out of lock in the vertical synchronization signal, the lock state is determined same as the horizontal synchronization signal. That is, output pulses of the frequency divider 54 are counted as a clock by the counter 60, and the lock state of the vertical synchronization signal is determined by the synchronization decision section 64 based on the counter value of the counter 60. In this practice, the internal HD and the external HD are input to the reset signal generating circuit 59. A reset signal is generated based on the corresponding signal timings and input to the reset terminal of the counter 60. As a result, the counter 60 is reset based on the timings of the internal HD and the external HD. The internal HD is the counted by the counter 60 and the counter value is input to the synchronization decision section 64. Output pulses of the VCO 53 may be counted in parallel by the counter 60.
In the synchronization decision section 64, the window setting circuit 61 sets the window period for determining the lock state and the decision circuit 62 references the count value at the leading edge of the external VD and determined whether the timing at the leading edge of the external VD is within a predetermined widow period in relation to the internal HD. In case the synchronization decision section 64 has detected that the timing of the external VD against the internal HD exceeded a predetermined range, the synchronization decision section 64 assumes that the vertical synchronization signal is out of synchronization and outputs an out-of-lock detection signal.
In case the H-system or V-system out-of-lock detection signal is output, it is determined that the video signal input is switched over and the horizontal or-vertical synchronization signal has gone out of synchronization. At this time, a video switchover detection signal is output from the output circuit 65. In this way, detection of video switchover is performed based on the lock state of the horizontal or vertical synchronization signal.
In the aforementioned related art video switchover detection circuit, in order to detect the phase dislocation amount of a synchronization signal against the internal HD as a reference signal, a window is set to determine whether the timing at the leading or trailing edge of an input signal is within the window period. Thus, a window setting circuit or a counter with a large-scale circuit is required to count the clock over the window period. This resulted in a complicated and large-scale circuit configuration. For example, in detecting H-system out of lock, a counter for counting the window period needs some 10 bits because the timing of the external HD may be earlier than that of the internal HD. A large number of count value is required in order to determine out of lock thus taking time to determine out of lock.
The invention has been proposed in consideration of the aforementioned circumstances and aims at providing a video switchover detection circuit that reduces the circuit scale and allows high-accuracy detection with a smaller-scale configuration.